Dependence of latch-up and threshold voltages on channel length in single-gated feedback field-effect transistor
DC Field | Value | Language |
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dc.contributor.author | Woo, Sola | - |
dc.contributor.author | Kim, Sangsig | - |
dc.date.accessioned | 2022-08-12T07:41:00Z | - |
dc.date.available | 2022-08-12T07:41:00Z | - |
dc.date.created | 2022-08-12 | - |
dc.date.issued | 2022-08-01 | - |
dc.identifier.issn | 0268-1242 | - |
dc.identifier.uri | https://scholar.korea.ac.kr/handle/2021.sw.korea/142883 | - |
dc.description.abstract | This study demonstrates an optimal design method for the channel length in a p (+)-i-p-n (+) structure of feedback field-effect transistors (FBFETs) for next-generation memory devices. We demonstrate the dependence of latch-up and threshold voltages on the channel length in single-gated FBFETs with silicon channels consisting of gated and non-gated regions. The operation principle of the latch-up phenomena related to the channel length using an equivalent circuit in an FBFET has been described. The abrupt increase in the drain current of the single-gated FBFETs at the latch-up (threshold) voltage in the sweep of the drain (gate) voltage was analyzed with current gains in an equivalent circuit. The current gain depends on the gated and non-gated channel lengths; thereby, the latch-up and threshold voltages too depend on the gated and non-gated channel lengths. The dependences of the latch-up and threshold voltages on the non-gated channel length were found to be 3.62 times and 1.68 times higher than that on the gated channel length, respectively. | - |
dc.language | English | - |
dc.language.iso | en | - |
dc.publisher | IOP Publishing Ltd | - |
dc.subject | OPERATION | - |
dc.subject | SIMULATION | - |
dc.subject | DESIGN | - |
dc.title | Dependence of latch-up and threshold voltages on channel length in single-gated feedback field-effect transistor | - |
dc.type | Article | - |
dc.contributor.affiliatedAuthor | Kim, Sangsig | - |
dc.identifier.doi | 10.1088/1361-6641/ac7b3e | - |
dc.identifier.scopusid | 2-s2.0-85134679968 | - |
dc.identifier.wosid | 000820875000001 | - |
dc.identifier.bibliographicCitation | SEMICONDUCTOR SCIENCE AND TECHNOLOGY, v.37, no.8 | - |
dc.relation.isPartOf | SEMICONDUCTOR SCIENCE AND TECHNOLOGY | - |
dc.citation.title | SEMICONDUCTOR SCIENCE AND TECHNOLOGY | - |
dc.citation.volume | 37 | - |
dc.citation.number | 8 | - |
dc.type.rims | ART | - |
dc.type.docType | Article | - |
dc.description.journalClass | 1 | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.relation.journalResearchArea | Engineering | - |
dc.relation.journalResearchArea | Materials Science | - |
dc.relation.journalResearchArea | Physics | - |
dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
dc.relation.journalWebOfScienceCategory | Materials Science, Multidisciplinary | - |
dc.relation.journalWebOfScienceCategory | Physics, Condensed Matter | - |
dc.subject.keywordPlus | OPERATION | - |
dc.subject.keywordPlus | SIMULATION | - |
dc.subject.keywordPlus | DESIGN | - |
dc.subject.keywordAuthor | feedback field-effect transistors | - |
dc.subject.keywordAuthor | latch-up mechanism | - |
dc.subject.keywordAuthor | latch-up voltage | - |
dc.subject.keywordAuthor | threshold voltage | - |
dc.subject.keywordAuthor | current gain | - |
dc.subject.keywordAuthor | channel length variation | - |
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