A New Compact CMOS Distributed Digital Attenuator
- Authors
- Park, Kwangwon; Lee, Seungjong; Jeon, Sanggeun
- Issue Date
- 11월-2020
- Publisher
- IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
- Keywords
- Attenuators; Attenuation; Transistors; Varistors; Insertion loss; Linearity; Topology; CMOS varistors; digital attenuator; distributed attenuator; millimeter wave (mm-wave); multistate cell; triple-well nFET
- Citation
- IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, v.68, no.11, pp.4631 - 4640
- Indexed
- SCIE
SCOPUS
- Journal Title
- IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES
- Volume
- 68
- Number
- 11
- Start Page
- 4631
- End Page
- 4640
- URI
- https://scholar.korea.ac.kr/handle/2021.sw.korea/51998
- DOI
- 10.1109/TMTT.2020.3017820
- ISSN
- 0018-9480
- Abstract
- This article presents a new millimeter-wave (mm-wave) distributed digital attenuator with a compact size and high linearity. To overcome the large area consumption of conventional distributed attenuators, multiple unit attenuation cells are combined at a single node, forming a multistate cell. By distributing the multistate cells along transmission lines (T-lines), the number of T-lines is reduced, leading to a compact chip size at a given attenuation range and step. The linearity is improved by stacking multiple FET varistors in each unit attenuation cell. An analytical analysis confirms that the proposed distributed attenuator topology maintains a low phase error comparable to that of the conventional counterpart. To experimentally verify the proposed topology, two different mm-wave digital attenuators are designed and implemented using a 65-nm CMOS technology. The first attenuator (Att1) uses a regular nFET as varistor of the attenuation cell, whereas the other attenuator (Att2_TW) uses a triple-well nFET to reduce the insertion loss. The maximum attenuation range of both attenuators is 14 dB with a step of 1 dB. The measured insertion losses of Att1 and Att2_TW are 4.8 and 4.1 dB at 35 GHz, respectively. The insertion losses are no more than 6.2 dB over 10-50 GHz and 4.3 dB over 15-43 GHz, respectively. The input 1-dB compression powers are 15 and 14 dBm, respectively, at 35 GHz. The chip sizes, excluding probing pads, are as small as 0.19 and 0.29 mm(2).
- Files in This Item
- There are no files associated with this item.
- Appears in
Collections - College of Engineering > School of Electrical Engineering > 1. Journal Articles
Items in ScholarWorks are protected by copyright, with all rights reserved, unless otherwise indicated.