WR-1.5 High-Power Frequency Doubler in 130-nm InP HBT Technology

Abstract

This letter presents a WR-1.5 frequency doubler implemented in a 130-nm InP heterojunction-bipolar-transistor (HBT) technology. The doubler core uses a differential common-emitter transistor to improve the stability and to ease the fundamental suppression. The output power is maximized by the source-pull and load-pull simulation. The input and output matching to the optimum impedance is implemented using a single transmission line. This simple matching structure reduces the modeling inaccuracy and the passive component loss at the terahertz frequencies. The output power of the doubler was measured in the frequency range of 590-610 GHz. The doubler exhibits the maximum output power of -5 dBm and conversion loss of 14 dB at 590 GHz without additional drive amplifiers.