Domain Wall Memory-Based Design of Deep Neural Network Convolutional Layers
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Chung, Jinil | - |
dc.contributor.author | Choi, Woong | - |
dc.contributor.author | Park, Jongsun | - |
dc.contributor.author | Ghosh, Swaroop | - |
dc.date.accessioned | 2021-08-31T16:08:38Z | - |
dc.date.available | 2021-08-31T16:08:38Z | - |
dc.date.created | 2021-06-18 | - |
dc.date.issued | 2020 | - |
dc.identifier.issn | 2169-3536 | - |
dc.identifier.uri | https://scholar.korea.ac.kr/handle/2021.sw.korea/59016 | - |
dc.description.abstract | In the hardware implementation of deep learning algorithms such as, convolutional neural networks (CNNs) and binarized neural networks (BNNs), multiple dot products and memories for storing parameters take a significant portion of area and power consumption. In this paper, we propose a domain wall memory (DWM) based design of CNN and BNN convolutional layers. In the proposed design, the resistive cell sensing mechanism is efficiently exploited to design low-cost DWM-based cell arrays for storing parameters. The unique serial access mechanism and small footprint of DWM are also used to reduce the area and energy cost of DWM-based design for filter sliding. Simulation results with 65 nm CMOS process show 45% and 43% of energy savings compared to the conventional CNN and BNN design approach, respectively. | - |
dc.language | English | - |
dc.language.iso | en | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.title | Domain Wall Memory-Based Design of Deep Neural Network Convolutional Layers | - |
dc.type | Article | - |
dc.contributor.affiliatedAuthor | Park, Jongsun | - |
dc.identifier.doi | 10.1109/ACCESS.2020.2968081 | - |
dc.identifier.scopusid | 2-s2.0-85079754546 | - |
dc.identifier.wosid | 000525389200009 | - |
dc.identifier.bibliographicCitation | IEEE ACCESS, v.8, pp.19783 - 19798 | - |
dc.relation.isPartOf | IEEE ACCESS | - |
dc.citation.title | IEEE ACCESS | - |
dc.citation.volume | 8 | - |
dc.citation.startPage | 19783 | - |
dc.citation.endPage | 19798 | - |
dc.type.rims | ART | - |
dc.type.docType | Article | - |
dc.description.journalClass | 1 | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.relation.journalResearchArea | Computer Science | - |
dc.relation.journalResearchArea | Engineering | - |
dc.relation.journalResearchArea | Telecommunications | - |
dc.relation.journalWebOfScienceCategory | Computer Science, Information Systems | - |
dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
dc.relation.journalWebOfScienceCategory | Telecommunications | - |
dc.subject.keywordAuthor | Binarized neural network | - |
dc.subject.keywordAuthor | convolutional neural network | - |
dc.subject.keywordAuthor | deep neural network | - |
dc.subject.keywordAuthor | domain wall memory | - |
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