Domain Wall Memory-Based Design of Deep Neural Network Convolutional Layers
- Authors
- Chung, Jinil; Choi, Woong; Park, Jongsun; Ghosh, Swaroop
- Issue Date
- 2020
- Publisher
- IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
- Keywords
- Binarized neural network; convolutional neural network; deep neural network; domain wall memory
- Citation
- IEEE ACCESS, v.8, pp.19783 - 19798
- Indexed
- SCIE
SCOPUS
- Journal Title
- IEEE ACCESS
- Volume
- 8
- Start Page
- 19783
- End Page
- 19798
- URI
- https://scholar.korea.ac.kr/handle/2021.sw.korea/59016
- DOI
- 10.1109/ACCESS.2020.2968081
- ISSN
- 2169-3536
- Abstract
- In the hardware implementation of deep learning algorithms such as, convolutional neural networks (CNNs) and binarized neural networks (BNNs), multiple dot products and memories for storing parameters take a significant portion of area and power consumption. In this paper, we propose a domain wall memory (DWM) based design of CNN and BNN convolutional layers. In the proposed design, the resistive cell sensing mechanism is efficiently exploited to design low-cost DWM-based cell arrays for storing parameters. The unique serial access mechanism and small footprint of DWM are also used to reduce the area and energy cost of DWM-based design for filter sliding. Simulation results with 65 nm CMOS process show 45% and 43% of energy savings compared to the conventional CNN and BNN design approach, respectively.
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Collections - College of Engineering > School of Electrical Engineering > 1. Journal Articles
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