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Investigation on dependency mechanism of inverter voltage gain on current level of photo stressed depletion mode thin-film transistors

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dc.contributor.authorLee, Byeong Hyeon-
dc.contributor.authorKim, Sangsig-
dc.contributor.authorLee, Sang Yeol-
dc.date.accessioned2021-09-01T13:59:15Z-
dc.date.available2021-09-01T13:59:15Z-
dc.date.created2021-06-19-
dc.date.issued2019-06-
dc.identifier.issn0038-1101-
dc.identifier.urihttps://scholar.korea.ac.kr/handle/2021.sw.korea/64850-
dc.description.abstractThe dependency of the inverter voltage gain on the current level (I-Level) of depletion mode (D-mode) thin-film transistors (TFTs) has been investigated with only n-type oxide semiconductor-based TFTs. It is clear that the voltage gain strongly depends on the D-mode I-Level. To investigate the dependency, photo stress was applied to the D-mode TFT to compare the inverter characteristics depending on the D-mode I-Level. As the photo stress time increased, the D-mode I-Level increased, and the voltage gains were degraded as a result. This was mainly because the I-Level of the D-mode is formed in the high section of the subthreshold slope (S.S) of the enhancement mode (E-mode) TFT when the photo stress was applied. By designing an inverter with a low D-mode I-Level, a high voltage gain of 9.85 was obtained at V-DD = 3 V. It is important to note that the S. S value of the E-mode and the I-Level of the D-mode should be optimized for high voltage gain for the application of next generation integrated circuits and highly sensitive photodetectors.-
dc.languageEnglish-
dc.language.isoen-
dc.publisherPERGAMON-ELSEVIER SCIENCE LTD-
dc.subjectCHANNEL LAYER THICKNESS-
dc.titleInvestigation on dependency mechanism of inverter voltage gain on current level of photo stressed depletion mode thin-film transistors-
dc.typeArticle-
dc.contributor.affiliatedAuthorKim, Sangsig-
dc.identifier.doi10.1016/j.sse.2019.03.030-
dc.identifier.scopusid2-s2.0-85063034489-
dc.identifier.wosid000464682900002-
dc.identifier.bibliographicCitationSOLID-STATE ELECTRONICS, v.156, pp.5 - 11-
dc.relation.isPartOfSOLID-STATE ELECTRONICS-
dc.citation.titleSOLID-STATE ELECTRONICS-
dc.citation.volume156-
dc.citation.startPage5-
dc.citation.endPage11-
dc.type.rimsART-
dc.type.docTypeArticle-
dc.description.journalClass1-
dc.description.journalRegisteredClassscie-
dc.description.journalRegisteredClassscopus-
dc.relation.journalResearchAreaEngineering-
dc.relation.journalResearchAreaPhysics-
dc.relation.journalWebOfScienceCategoryEngineering, Electrical & Electronic-
dc.relation.journalWebOfScienceCategoryPhysics, Applied-
dc.relation.journalWebOfScienceCategoryPhysics, Condensed Matter-
dc.subject.keywordPlusCHANNEL LAYER THICKNESS-
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공과대학 (전기전자공학부)
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