Investigation on dependency mechanism of inverter voltage gain on current level of photo stressed depletion mode thin-film transistors
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Lee, Byeong Hyeon | - |
dc.contributor.author | Kim, Sangsig | - |
dc.contributor.author | Lee, Sang Yeol | - |
dc.date.accessioned | 2021-09-01T13:59:15Z | - |
dc.date.available | 2021-09-01T13:59:15Z | - |
dc.date.created | 2021-06-19 | - |
dc.date.issued | 2019-06 | - |
dc.identifier.issn | 0038-1101 | - |
dc.identifier.uri | https://scholar.korea.ac.kr/handle/2021.sw.korea/64850 | - |
dc.description.abstract | The dependency of the inverter voltage gain on the current level (I-Level) of depletion mode (D-mode) thin-film transistors (TFTs) has been investigated with only n-type oxide semiconductor-based TFTs. It is clear that the voltage gain strongly depends on the D-mode I-Level. To investigate the dependency, photo stress was applied to the D-mode TFT to compare the inverter characteristics depending on the D-mode I-Level. As the photo stress time increased, the D-mode I-Level increased, and the voltage gains were degraded as a result. This was mainly because the I-Level of the D-mode is formed in the high section of the subthreshold slope (S.S) of the enhancement mode (E-mode) TFT when the photo stress was applied. By designing an inverter with a low D-mode I-Level, a high voltage gain of 9.85 was obtained at V-DD = 3 V. It is important to note that the S. S value of the E-mode and the I-Level of the D-mode should be optimized for high voltage gain for the application of next generation integrated circuits and highly sensitive photodetectors. | - |
dc.language | English | - |
dc.language.iso | en | - |
dc.publisher | PERGAMON-ELSEVIER SCIENCE LTD | - |
dc.subject | CHANNEL LAYER THICKNESS | - |
dc.title | Investigation on dependency mechanism of inverter voltage gain on current level of photo stressed depletion mode thin-film transistors | - |
dc.type | Article | - |
dc.contributor.affiliatedAuthor | Kim, Sangsig | - |
dc.identifier.doi | 10.1016/j.sse.2019.03.030 | - |
dc.identifier.scopusid | 2-s2.0-85063034489 | - |
dc.identifier.wosid | 000464682900002 | - |
dc.identifier.bibliographicCitation | SOLID-STATE ELECTRONICS, v.156, pp.5 - 11 | - |
dc.relation.isPartOf | SOLID-STATE ELECTRONICS | - |
dc.citation.title | SOLID-STATE ELECTRONICS | - |
dc.citation.volume | 156 | - |
dc.citation.startPage | 5 | - |
dc.citation.endPage | 11 | - |
dc.type.rims | ART | - |
dc.type.docType | Article | - |
dc.description.journalClass | 1 | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.relation.journalResearchArea | Engineering | - |
dc.relation.journalResearchArea | Physics | - |
dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
dc.relation.journalWebOfScienceCategory | Physics, Applied | - |
dc.relation.journalWebOfScienceCategory | Physics, Condensed Matter | - |
dc.subject.keywordPlus | CHANNEL LAYER THICKNESS | - |
Items in ScholarWorks are protected by copyright, with all rights reserved, unless otherwise indicated.
(02841) 서울특별시 성북구 안암로 14502-3290-1114
COPYRIGHT © 2021 Korea University. All Rights Reserved.
Certain data included herein are derived from the © Web of Science of Clarivate Analytics. All rights reserved.
You may not copy or re-distribute this material in whole or in part without the prior written consent of Clarivate Analytics.