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Impact of Random Dopant Fluctuation on n-Type Ge Junctionless FinFETs With Metal-Interlayer-Semiconductor Source/Drain Contact Structure

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dc.contributor.authorJung, Seung-Geun-
dc.contributor.authorYu, Hyun-Yong-
dc.date.accessioned2021-09-01T22:41:43Z-
dc.date.available2021-09-01T22:41:43Z-
dc.date.created2021-06-19-
dc.date.issued2019-
dc.identifier.issn2168-6734-
dc.identifier.urihttps://scholar.korea.ac.kr/handle/2021.sw.korea/68893-
dc.description.abstractThe impact of random dopant fluctuation (RDF) on n-type Ge junctionless FinFETs (JLFETs) with metal-interlayer-semiconductor (MIS) source/drain (S/D) contact structure is firstly investigated via 3-D technology computer aided design (TCAD) simulations. The estimation and evaluation of standard deviations in threshold voltage (V-th), on-state current (I-on), off-state current (I-off), subthreshold swing (SS), and drain induced barrier lowering (DIBL) by different Ge nanowire doping concentrations and different heights for RDF effects are performed. The results show a decreasing trend of RDF with lower doping concentration of the device. Furthermore, the influence of MIS S/D on RDF of n-type Ge JLFET is assessed through a comparative analysis between an n-type Ge JLFETs with and without MIS S/D structure. The analysis results estimate that MIS S/D can reduce performance variation to approximately 0.0237 V for sigma Vth, 5.75 x 10(-5) A/um for sigma I-on, 4.30 x 10(-1)0 A/um for sigma I-off,I- 0.548 mV/dec for sigma SS, and 12.3 mV/V for DIBL, without severe performance degradation of the current nominal values. This estimation gives a significant insight on variability prediction of the 7 nm n-type Ge JLFET device with MIS S/D structure.-
dc.languageEnglish-
dc.language.isoen-
dc.publisherIEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC-
dc.subjectFIELD-EFFECT TRANSISTOR-
dc.subjectPERFORMANCE-
dc.titleImpact of Random Dopant Fluctuation on n-Type Ge Junctionless FinFETs With Metal-Interlayer-Semiconductor Source/Drain Contact Structure-
dc.typeArticle-
dc.contributor.affiliatedAuthorYu, Hyun-Yong-
dc.identifier.doi10.1109/JEDS.2019.2949566-
dc.identifier.scopusid2-s2.0-85074540316-
dc.identifier.wosid000497758500002-
dc.identifier.bibliographicCitationIEEE JOURNAL OF THE ELECTRON DEVICES SOCIETY, v.7, no.1, pp.1119 - 1124-
dc.relation.isPartOfIEEE JOURNAL OF THE ELECTRON DEVICES SOCIETY-
dc.citation.titleIEEE JOURNAL OF THE ELECTRON DEVICES SOCIETY-
dc.citation.volume7-
dc.citation.number1-
dc.citation.startPage1119-
dc.citation.endPage1124-
dc.type.rimsART-
dc.type.docTypeArticle-
dc.description.journalClass1-
dc.description.journalRegisteredClassscie-
dc.description.journalRegisteredClassscopus-
dc.relation.journalResearchAreaEngineering-
dc.relation.journalWebOfScienceCategoryEngineering, Electrical & Electronic-
dc.subject.keywordPlusFIELD-EFFECT TRANSISTOR-
dc.subject.keywordPlusPERFORMANCE-
dc.subject.keywordAuthorJunctionless FET-
dc.subject.keywordAuthorgermanium-
dc.subject.keywordAuthormetal-inter layer-semiconductor source-
dc.subject.keywordAuthordrain-
dc.subject.keywordAuthor3-D TCAD-
dc.subject.keywordAuthorrandom dopant fluctuation (RDF)-
dc.subject.keywordAuthorline-edge roughness (LER)-
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