A 283-GHz Fully Integrated Phase-Locked Loop Based on 65-nm CMOS
DC Field | Value | Language |
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dc.contributor.author | Yoo, Junghwan | - |
dc.contributor.author | Kim, Doyoon | - |
dc.contributor.author | Kim, Jungsoo | - |
dc.contributor.author | Song, Kiryong | - |
dc.contributor.author | Rieh, Jae-Sung | - |
dc.date.accessioned | 2021-09-02T04:07:51Z | - |
dc.date.available | 2021-09-02T04:07:51Z | - |
dc.date.created | 2021-06-19 | - |
dc.date.issued | 2018-11 | - |
dc.identifier.issn | 2156-342X | - |
dc.identifier.uri | https://scholar.korea.ac.kr/handle/2021.sw.korea/71922 | - |
dc.description.abstract | A 283-GHz fully integrated phase-locked loop (PLL) based on a 65-nm CMOS technology is presented. A triple-push ring voltage-controlled oscillator and a frequency divider chain (/16,384) composed of 2 injection-locked frequency dividers are developed, which are integrated with 12 current-mode logic frequency dividers, a phase frequency detector, a charge pump, and a loop filte. The fabricated PLL showed a locking range of 282.3-283.7 GHz and a phase noise of-53.5 dBc/Hz at 100 kHz (in band) and -78.6 dBc/Hz at 10 MHz (out of band). Total dc power consumption is 114 mW. The chip occupies 920 x 520 mu m(2) excluding probing pads. | - |
dc.language | English | - |
dc.language.iso | en | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.subject | RECEIVER | - |
dc.subject | LOCKING | - |
dc.title | A 283-GHz Fully Integrated Phase-Locked Loop Based on 65-nm CMOS | - |
dc.type | Article | - |
dc.contributor.affiliatedAuthor | Rieh, Jae-Sung | - |
dc.identifier.doi | 10.1109/TTHZ.2018.2875796 | - |
dc.identifier.scopusid | 2-s2.0-85055032227 | - |
dc.identifier.wosid | 000453572200028 | - |
dc.identifier.bibliographicCitation | IEEE TRANSACTIONS ON TERAHERTZ SCIENCE AND TECHNOLOGY, v.8, no.6, pp.784 - 792 | - |
dc.relation.isPartOf | IEEE TRANSACTIONS ON TERAHERTZ SCIENCE AND TECHNOLOGY | - |
dc.citation.title | IEEE TRANSACTIONS ON TERAHERTZ SCIENCE AND TECHNOLOGY | - |
dc.citation.volume | 8 | - |
dc.citation.number | 6 | - |
dc.citation.startPage | 784 | - |
dc.citation.endPage | 792 | - |
dc.type.rims | ART | - |
dc.type.docType | Article | - |
dc.description.journalClass | 1 | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.relation.journalResearchArea | Engineering | - |
dc.relation.journalResearchArea | Optics | - |
dc.relation.journalResearchArea | Physics | - |
dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
dc.relation.journalWebOfScienceCategory | Optics | - |
dc.relation.journalWebOfScienceCategory | Physics, Applied | - |
dc.subject.keywordPlus | RECEIVER | - |
dc.subject.keywordPlus | LOCKING | - |
dc.subject.keywordAuthor | CMOS integrated circuits | - |
dc.subject.keywordAuthor | frequency synthesizer | - |
dc.subject.keywordAuthor | phase-locked loop (PLL) | - |
dc.subject.keywordAuthor | ring oscillator | - |
dc.subject.keywordAuthor | voltage-controlled oscillator (VCO) | - |
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