A 283-GHz Fully Integrated Phase-Locked Loop Based on 65-nm CMOS
- Authors
- Yoo, Junghwan; Kim, Doyoon; Kim, Jungsoo; Song, Kiryong; Rieh, Jae-Sung
- Issue Date
- 11월-2018
- Publisher
- IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
- Keywords
- CMOS integrated circuits; frequency synthesizer; phase-locked loop (PLL); ring oscillator; voltage-controlled oscillator (VCO)
- Citation
- IEEE TRANSACTIONS ON TERAHERTZ SCIENCE AND TECHNOLOGY, v.8, no.6, pp.784 - 792
- Indexed
- SCIE
SCOPUS
- Journal Title
- IEEE TRANSACTIONS ON TERAHERTZ SCIENCE AND TECHNOLOGY
- Volume
- 8
- Number
- 6
- Start Page
- 784
- End Page
- 792
- URI
- https://scholar.korea.ac.kr/handle/2021.sw.korea/71922
- DOI
- 10.1109/TTHZ.2018.2875796
- ISSN
- 2156-342X
- Abstract
- A 283-GHz fully integrated phase-locked loop (PLL) based on a 65-nm CMOS technology is presented. A triple-push ring voltage-controlled oscillator and a frequency divider chain (/16,384) composed of 2 injection-locked frequency dividers are developed, which are integrated with 12 current-mode logic frequency dividers, a phase frequency detector, a charge pump, and a loop filte. The fabricated PLL showed a locking range of 282.3-283.7 GHz and a phase noise of-53.5 dBc/Hz at 100 kHz (in band) and -78.6 dBc/Hz at 10 MHz (out of band). Total dc power consumption is 114 mW. The chip occupies 920 x 520 mu m(2) excluding probing pads.
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