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A Simple Method for Estimation of Silicon Film Thickness in T-Gate Junction less Transistors
- Authors
- Jeon, Dae-Young; Park, So Jeong; Mouis, Mireille; Barraud, Sylvain; Kim, Gyu-Tae; Ghibaudo, Gerard
- Issue Date
- Sep-2018
- Publisher
- IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
- Keywords
- Junctionless transistors (JLTs); Si thickness (t(si)); bulk neutral channel; surface accumulation channel; method for parameter extraction; numerical simulation
- Citation
- IEEE ELECTRON DEVICE LETTERS, v.39, no.9, pp.1282 - 1285
- Indexed
- SCIE
SCOPUS
- Journal Title
- IEEE ELECTRON DEVICE LETTERS
- Volume
- 39
- Number
- 9
- Start Page
- 1282
- End Page
- 1285
- ISSN
- 0741-3106
- Abstract
- Junction less transistors (JLTs) without PN-junctions near the source/drain are promising candidates for further development of CMOS technology. The Si thickness of tri-gate JLTs is crucial to understand their unique electrical properties related to bulk neutral and surface accumulation conduction. A simple method based on a unique operation mechanism is suggested for extraction of t(si) from measurements on tri-gate JLTs. The method was successfully applied to fabricated tri-gate JLTs and the extracted t(si) values were comparable with those of transmission electron microscopy. Furthermore, the validity of the method was confirmed by 2-D numerical simulation.
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Related Researcher
- Kim, Gyu Tae
- College of Engineering (School of Electrical Engineering)