Effects of Metal-Interlayer-Semiconductor Source/Drain Contact Structure on n-Type Germanium Junctionless FinFETs

Abstract

In this paper, the effects of a metalinterlayer- semiconductor (MIS) source/drain (S/D) structure with a heavily doped interlayer on enhancement-mode n-type germanium (Ge) junctionless FinFETs (JLFETs) are demonstrated via 3-D technology computer aided design simulation. N-type Ge JLFETs using metal-semiconductor (MS) S/D structures face difficulty in operating in the enhancement mode, as severe Fermi-level pinning (FLP) triggers extremely high off-state current (IOFF) and extremely low on-state current (ION). The MIS S/D structure can solve these problemsbymitigatingFLP. In the simulation of an n-type Ge JLFET with the MIS S/D structure, IOFF of 9.42x10(-10) A/mu m, ION of 6.09x10(-4) A/mu m, and subthreshold slope of 65.38mV/dec are achieved. The performance of the device for different channel-doping concentrations and fin dimensions is also evaluated. Thus, anMIS S/D structure with a heavily doped interlayer can effectively strengthen the performances of n-typeGe JLFETs beyond the sub-7-nm technology node.