합성곱 신경망을 이용한 웨이퍼 맵 기반 불량 탐지

Abstract

The Electrical die sorting (EDS) test is performed to discriminate defective wafers for the purpose of improving the yield of the wafers during the semiconductor manufacturing process, and wafer maps are generated as a result. Semiconductor manufacturing process and equipment engineers use the patterns of the wafer map based on their knowledge to judge the defective wafer and estimate the cause. We use convolutional neural network which demonstrate good performance in the image classification. The convolutional neural network is used as a classification model of which the image of wafer map itself as input and whether the image is good or bad as output. While previous studies have used hand-crafted features for wafer map-based fault detection, the methodology used in this study is that the convolutional neural network learns the features useful for classification, it has the advantage of integrating knowledge. We show that the proposed classifier has better prediction accuracy than the conventional machine learning based techniques such as multilayer perceptron and random forest empirically by experiments on the data collected in the actual semiconductor manufacturing process.