A 1.62-5.4-Gb/s Receiver for DisplayPort Version 1.2a With Adaptive Equalization and Referenceless Frequency Acquisition Techniques
- Authors
- Hwang, Sewook; Song, Junyoung; Lee, Yeonho; Kim, Chulwoo
- Issue Date
- 10월-2017
- Publisher
- IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
- Keywords
- Receiver (Rx); adaptive equalizer (EQ); referenceless; clock and data recovery (CDR); frequency detector; DisplayPort; compliance test
- Citation
- IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, v.64, no.10, pp.2691 - 2702
- Indexed
- SCIE
SCOPUS
- Journal Title
- IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS
- Volume
- 64
- Number
- 10
- Start Page
- 2691
- End Page
- 2702
- URI
- https://scholar.korea.ac.kr/handle/2021.sw.korea/82157
- DOI
- 10.1109/TCSI.2017.2695612
- ISSN
- 1549-8328
- Abstract
- We present a 1.62-5.4-Gb/s receiver for DisplayPort version 1.2a and propose an adaptive equalizer (EQ) with a peak-level comparison technique for eye measurement. A single comparator and an up/down unmatched-current charge pump are used to realize a simpler EQ architecture with low power dissipation. A referenceless frequency acquisition technique is also proposed. A time-to-digital converter-based pulsewidth detector supports the referenceless frequency acquisition within the range of 1.62-5.4 Gb/s. An XOR-gate-embedded charge pump and a half-rate linear phase detector were used to improve the jitter tolerance (JTOL) performance. The measured eye opening of the proposed EQ at 5.4 Gb/s was 0.68 UI with a -20-dB loss channel. The proposed receiver passed all the JTOL tests of the DisplayPort compliance specification version 1.2b. The power consumption of the receiver was 36.8 mW at 5.4 Gb/s. The receiver occupied a core area of 0.265 mm(2) using 65-nm CMOS process technology.
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