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A 1.3V input fast-transient-response time digital low-dropout regulator with a VSSa generator for DVFS system
- Issue Date
- 10-7월-2017
- Publisher
- IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG
- Keywords
- low-dropout (LDO) regulator; digital low-dropout (D-LDO) regulator; fast-transient-response time; dynamic voltage frequency scaling (DVFS)
- Citation
- IEICE ELECTRONICS EXPRESS, v.14, no.13
- Indexed
- SCIE
SCOPUS
- Journal Title
- IEICE ELECTRONICS EXPRESS
- Volume
- 14
- Number
- 13
- ISSN
- 1349-2543
- Abstract
- A fast transient-response digital low-dropout regulator ( D-LDO) is presented. To achieve fast-transient time, a VSSa generator and a coarse-fine power-MOS array techniques are proposed. The proposed D-LDO is implemented in a 65 nm CMOS technology with a die area of 0.067 mm(2). The measured recovery time is less than 0.32 us when the load step-up time is 0.1 us from 2.5mA to 120 mA, and the step-down time is 0.1 us at 1.2V of supply voltage. Moreover, the voltage spikes are less than 190mV.
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