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Optimal Memory Size Formula for Moving-Average Digital Phase-Locked Loop

Authors
Ahn, Choon KiShi, PengYou, Sung Hyun
Issue Date
12월-2016
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Keywords
Digital phase-locked loop (DPLL); moving average; optimal memory size; robustness; unbiasedness
Citation
IEEE SIGNAL PROCESSING LETTERS, v.23, no.12, pp.1844 - 1847
Indexed
SCIE
SCOPUS
Journal Title
IEEE SIGNAL PROCESSING LETTERS
Volume
23
Number
12
Start Page
1844
End Page
1847
URI
https://scholar.korea.ac.kr/handle/2021.sw.korea/86623
DOI
10.1109/LSP.2016.2623520
ISSN
1070-9908
Abstract
This letter proposes a new moving-average form of digital phase-locked loop (DPLL) that uses the average value of measurements on a memory horizon and the correction term to estimate phase information. This ensures the desired unbiasedness property for the phase information. A new formula for the optimal memory size of the proposed DPLL with minimization of the expected squared phase error is established. A numerical example is given to show that the developed DPLL has superior robustness against quantization and incorrect noise compared to the existing DPLLs.
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공과대학 (전기전자공학부)
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