A 4 x 5-Gb/s 1.12-mu s Locking Time Reference-Less Receiver With Asynchronous Sampling-Based Frequency Acquisition and Clock Shared Subchannels
- Authors
- Song, Junyoung; Hwang, Sewook; Kim, Chulwoo
- Issue Date
- 8월-2016
- Publisher
- IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
- Keywords
- Clock and data recovery (CDR); deskew algorithm; frequency detection; multichannel interface; referenceless receiver; VCO calibration
- Citation
- IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, v.24, no.8, pp.2768 - 2777
- Indexed
- SCIE
SCOPUS
- Journal Title
- IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
- Volume
- 24
- Number
- 8
- Start Page
- 2768
- End Page
- 2777
- URI
- https://scholar.korea.ac.kr/handle/2021.sw.korea/87930
- DOI
- 10.1109/TVLSI.2016.2520584
- ISSN
- 1063-8210
- Abstract
- A 4x5-Gb/s reference-less receiver is proposed in a 0.13-mu m CMOS technology. In the proposed reference-less clock and data recovery (CDR) circuit, asynchronous sampling-based frequency acquisition is proposed to achieve a fast frequency locking, and VCO calibration is proposed to attain a constant loop bandwidth. To reduce noise caused by multiple VCOs, a clock signal is forwarded from the main channel to the subchannels, and skews between the channels are compensated by a skew compensation algorithm. In the main channel, the reference-less CDR achieves a 1.12-mu s locking time, and the measured standard deviation of VCO gain is reduced from 0.33 to 0.08. The recovered clock jitter in the main channel is 1.591 ps(rms), and the power consumption of the main channel and the subchannels are 3.53 and 2.16 mW/Gb/s, respectively.
- Files in This Item
- There are no files associated with this item.
- Appears in
Collections - College of Engineering > School of Electrical Engineering > 1. Journal Articles
Items in ScholarWorks are protected by copyright, with all rights reserved, unless otherwise indicated.