Two 122-GHz Phase-Locked Loops in 65-nm CMOS Technology
DC Field | Value | Language |
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dc.contributor.author | Kim, Namhyung | - |
dc.contributor.author | Song, Kiryong | - |
dc.contributor.author | Yun, Jongwon | - |
dc.contributor.author | Yoo, Junghwan | - |
dc.contributor.author | Rieh, Jae-Sung | - |
dc.date.accessioned | 2021-09-03T21:35:28Z | - |
dc.date.available | 2021-09-03T21:35:28Z | - |
dc.date.created | 2021-06-18 | - |
dc.date.issued | 2016-08 | - |
dc.identifier.issn | 0018-9480 | - |
dc.identifier.uri | https://scholar.korea.ac.kr/handle/2021.sw.korea/87986 | - |
dc.description.abstract | Two 122-GHz phase-locked loops (PLLs) have been developed based on a 65-nm Si CMOS technology, and their performances are compared. For the first PLL, a voltage-controlled oscillator (VCO) with a frequency doubler embedded in the oscillator core was employed (PLL1), while the second PLL employs a push-push VCO (PLL2). The output powers of PLL1 and PLL2 were -8.6 and -21.9 dBm near 122 GHz, obtained from dc power dissipation of 82.9 and 87.7 mW, respectively. The respective locking ranges were measured to be 121.9-122.2 and 122.7-122.9 GHz for PLL1 and PLL2. The in-band phase noises were -59.2 and -60.1 dBc/Hz at 10-kHz offset, and the out-band phase noises were -102.4 and -99.5 dBc/Hz at 10-MHz offset for PLL1 and PLL2, respectively. The chip sizes were 1000 x 760 mu m(2) (PLL1) and 1300 x 840 mu m(2) (PLL2) including probing pads. | - |
dc.language | English | - |
dc.language.iso | en | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.subject | GHZ | - |
dc.title | Two 122-GHz Phase-Locked Loops in 65-nm CMOS Technology | - |
dc.type | Article | - |
dc.contributor.affiliatedAuthor | Rieh, Jae-Sung | - |
dc.identifier.doi | 10.1109/TMTT.2016.2581816 | - |
dc.identifier.scopusid | 2-s2.0-84978955103 | - |
dc.identifier.wosid | 000384142200028 | - |
dc.identifier.bibliographicCitation | IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, v.64, no.8, pp.2623 - 2630 | - |
dc.relation.isPartOf | IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES | - |
dc.citation.title | IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES | - |
dc.citation.volume | 64 | - |
dc.citation.number | 8 | - |
dc.citation.startPage | 2623 | - |
dc.citation.endPage | 2630 | - |
dc.type.rims | ART | - |
dc.type.docType | Article | - |
dc.description.journalClass | 1 | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.relation.journalResearchArea | Engineering | - |
dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
dc.subject.keywordPlus | GHZ | - |
dc.subject.keywordAuthor | Phase noise | - |
dc.subject.keywordAuthor | phase-locked loop (PLL) | - |
dc.subject.keywordAuthor | voltage-controlled oscillator (VCO) | - |
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