Two 122-GHz Phase-Locked Loops in 65-nm CMOS Technology
- Authors
- Kim, Namhyung; Song, Kiryong; Yun, Jongwon; Yoo, Junghwan; Rieh, Jae-Sung
- Issue Date
- 8월-2016
- Publisher
- IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
- Keywords
- Phase noise; phase-locked loop (PLL); voltage-controlled oscillator (VCO)
- Citation
- IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, v.64, no.8, pp.2623 - 2630
- Indexed
- SCIE
SCOPUS
- Journal Title
- IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES
- Volume
- 64
- Number
- 8
- Start Page
- 2623
- End Page
- 2630
- URI
- https://scholar.korea.ac.kr/handle/2021.sw.korea/87986
- DOI
- 10.1109/TMTT.2016.2581816
- ISSN
- 0018-9480
- Abstract
- Two 122-GHz phase-locked loops (PLLs) have been developed based on a 65-nm Si CMOS technology, and their performances are compared. For the first PLL, a voltage-controlled oscillator (VCO) with a frequency doubler embedded in the oscillator core was employed (PLL1), while the second PLL employs a push-push VCO (PLL2). The output powers of PLL1 and PLL2 were -8.6 and -21.9 dBm near 122 GHz, obtained from dc power dissipation of 82.9 and 87.7 mW, respectively. The respective locking ranges were measured to be 121.9-122.2 and 122.7-122.9 GHz for PLL1 and PLL2. The in-band phase noises were -59.2 and -60.1 dBc/Hz at 10-kHz offset, and the out-band phase noises were -102.4 and -99.5 dBc/Hz at 10-MHz offset for PLL1 and PLL2, respectively. The chip sizes were 1000 x 760 mu m(2) (PLL1) and 1300 x 840 mu m(2) (PLL2) including probing pads.
- Files in This Item
- There are no files associated with this item.
- Appears in
Collections - College of Engineering > School of Electrical Engineering > 1. Journal Articles
Items in ScholarWorks are protected by copyright, with all rights reserved, unless otherwise indicated.