Threshold voltage variation-immune FinFET design with metal-interlayer-semiconductor source/drain structure
DC Field | Value | Language |
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dc.contributor.author | Shin, Changho | - |
dc.contributor.author | Kim, Jeong-Kyu | - |
dc.contributor.author | Shin, Changhwan | - |
dc.contributor.author | Kim, Jong-Kook | - |
dc.contributor.author | Yu, Hyun-Yong | - |
dc.date.accessioned | 2021-09-03T23:11:07Z | - |
dc.date.available | 2021-09-03T23:11:07Z | - |
dc.date.created | 2021-06-18 | - |
dc.date.issued | 2016-06 | - |
dc.identifier.issn | 1567-1739 | - |
dc.identifier.uri | https://scholar.korea.ac.kr/handle/2021.sw.korea/88412 | - |
dc.description.abstract | The impact of random dopant fluctuation (RDF) on a 10-nm n-type silicon (Si) FinFET with a metal-insulator-semiconductor (M-I-S) source/drain (S/D) structure is investigated using three-dimensional TCAD simulation. To determine the optimal aspect ratio of the fin for a variation-robust FinFET with an M-I-S S/D structure, various metrics for device performance are quantitatively evaluated. It is found that variation in RDF-induced threshold voltage (V-th) in the FinFET can be suppressed with a taller fin (i.e., a fin with a higher aspect ratio) because of better gate-to-channel controllability and wider channel width. For a fin aspect ratio (i.e., fin height to fin width) of 5.25:1, the standard deviation for RDF-induced V-th in a FinFET with an S/D doping concentration (N-S/D) of 5 x 10(20) cm(-3) is 9.277 mV. In order to suppress RDF-induced V-th variation even further, an M-I-S structure with a heavily doped n-type ZnO interlayer can be introduced into the S/D region of the FinFET. For the tallest fin height, this M-I-S S/D structure (with an N-S/D = 5 x 10(19) cm(-3)) results in a standard deviation of 4.729 mV for RDF-induced V-th, while maintaining the on-state drive current (I-on) at a satisfactory level. Therefore, it is expected that a 10-nm n-type FinFET can be designed to be immune to Vth variation with the adoption of the proposed M-I-S S/D structure. (C) 2016 Elsevier B.V. All rights reserved. | - |
dc.language | English | - |
dc.language.iso | en | - |
dc.publisher | ELSEVIER | - |
dc.subject | FLUCTUATION | - |
dc.title | Threshold voltage variation-immune FinFET design with metal-interlayer-semiconductor source/drain structure | - |
dc.type | Article | - |
dc.contributor.affiliatedAuthor | Kim, Jong-Kook | - |
dc.contributor.affiliatedAuthor | Yu, Hyun-Yong | - |
dc.identifier.doi | 10.1016/j.cap.2016.03.006 | - |
dc.identifier.scopusid | 2-s2.0-84962227279 | - |
dc.identifier.wosid | 000374659600002 | - |
dc.identifier.bibliographicCitation | CURRENT APPLIED PHYSICS, v.16, no.6, pp.618 - 622 | - |
dc.relation.isPartOf | CURRENT APPLIED PHYSICS | - |
dc.citation.title | CURRENT APPLIED PHYSICS | - |
dc.citation.volume | 16 | - |
dc.citation.number | 6 | - |
dc.citation.startPage | 618 | - |
dc.citation.endPage | 622 | - |
dc.type.rims | ART | - |
dc.type.docType | Article | - |
dc.identifier.kciid | ART002116847 | - |
dc.description.journalClass | 1 | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.description.journalRegisteredClass | kci | - |
dc.relation.journalResearchArea | Materials Science | - |
dc.relation.journalResearchArea | Physics | - |
dc.relation.journalWebOfScienceCategory | Materials Science, Multidisciplinary | - |
dc.relation.journalWebOfScienceCategory | Physics, Applied | - |
dc.subject.keywordPlus | FLUCTUATION | - |
dc.subject.keywordAuthor | CMOS | - |
dc.subject.keywordAuthor | FinFET | - |
dc.subject.keywordAuthor | Metal-interlayer-semiconductor | - |
dc.subject.keywordAuthor | Random dopant fluctuation | - |
dc.subject.keywordAuthor | Variation | - |
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