An Add-On Type Real-Time Jitter Tolerance Enhancer for Digital Communication Receivers
- Authors
- Hwang, Sewook; Song, Junyoung; Bae, Sang-Geun; Lee, Yeonho; Kim, Chulwoo
- Issue Date
- 3월-2016
- Publisher
- IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
- Keywords
- Bit error rate (BER); jitter tolerance (JTOL); real-time jitter tolerance enhancer (JTE); receiver (Rx)
- Citation
- IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, v.24, no.3, pp.1092 - 1103
- Indexed
- SCIE
SCOPUS
- Journal Title
- IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
- Volume
- 24
- Number
- 3
- Start Page
- 1092
- End Page
- 1103
- URI
- https://scholar.korea.ac.kr/handle/2021.sw.korea/89382
- DOI
- 10.1109/TVLSI.2015.2435026
- ISSN
- 1063-8210
- Abstract
- An add-on type real-time jitter tolerance enhancer (JTE) is presented in this paper. The proposed JTE can improve high-frequency jitter tolerance (JTOL) by using a real-time phase alignment scheme. A mathematical analysis for an advanced bit error rate (BER) prediction method is also introduced. The proposed circuit is applicable to various types of receivers, such as referenceless receivers, receivers with a reference clock source, and source-synchronous receivers. The referenceless receiver with the proposed JTE achieved an out-of-band JTOL of 0.71 UIpp at 100 MHz with <10(-12) BER. This is 196% higher than a conventional receiver without the JTE. The source-synchronous receiver with the proposed JTE achieved 0.92 UIpp at 300 MHz with <10(-12) BER. Total core areas of the receiver and JTE are 0.19 and 0.07 mm(2) in a 0.13-mu m CMOS process, respectively. The power consumption of the receiver is 38 mW at 5.4 Gbit/s, and the JTE dissipates 22 mW.
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Collections - College of Engineering > School of Electrical Engineering > 1. Journal Articles
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