All-Digital Duty-Cycle Corrector With a Wide Duty Correction Range for DRAM Applications
- Authors
- Jeong, Chan-Hui; Abdullah, Ammar; Min, Young-Jae; Hwang, In-Chul; Kim, Soo-Won
- Issue Date
- 1월-2016
- Publisher
- IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
- Keywords
- DRAM; duty-cycle corrector (DCC); successive approximation register (SAR) controller; Digital comparator; double data rate
- Citation
- IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, v.24, no.1, pp.363 - 367
- Indexed
- SCIE
SCOPUS
- Journal Title
- IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
- Volume
- 24
- Number
- 1
- Start Page
- 363
- End Page
- 367
- URI
- https://scholar.korea.ac.kr/handle/2021.sw.korea/90005
- DOI
- 10.1109/TVLSI.2015.2394486
- ISSN
- 1063-8210
- Abstract
- An all-digital duty-cycle corrector with a wide duty correction range and fast correction time is hereby presented. The proposed corrector uses a 1-bit digital duty-cycle detector with a time-to-digital converter, and it achieves a duty correction range between 10% and 90% with a low pressure, volume, and temperature variation. The test chip was fabricated using a 0.13-mu m CMOS process, and it occupies an area of 0.059 mm(2). The correction cycle is a 14 cycles and the duty-cycle error is below +/- 1.4%. At an operating frequency of 1 GHz, the power dissipation and peak-to-peak jitter are measured at 5.6 mW and 20.5 ps, respectively.
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- Appears in
Collections - College of Engineering > School of Electrical Engineering > 1. Journal Articles
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