A 6-bit 2.5-GS/s Time-Interleaved Analog-to-Digital Converter Using Resistor-Array Sharing Digital-to-Analog Converter
- Authors
- Lee, Hokyu; Aurangozeb; Park, Sejin; Kim, Jintae; Kim, Chulwoo
- Issue Date
- 11월-2015
- Publisher
- IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
- Keywords
- Analog-to-digital converter (ADC); calibration; input folding; resistive digital-to-analog converter (RDAC); successive approximation register (SAR); time-interleaving (TI)
- Citation
- IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, v.23, no.11, pp.2371 - 2383
- Indexed
- SCIE
SCOPUS
- Journal Title
- IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
- Volume
- 23
- Number
- 11
- Start Page
- 2371
- End Page
- 2383
- URI
- https://scholar.korea.ac.kr/handle/2021.sw.korea/92073
- DOI
- 10.1109/TVLSI.2014.2372033
- ISSN
- 1063-8210
- Abstract
- This paper presents a 6-bit 2.5-GS/s time-interleaved (TI) successive-approximation-register (SAR) analog-to-digital converter (ADC) that uses a resistor-array sharing digital-to-analog converter (RASD). By applying the input folding technique in the input stage and utilizing the flash-assisted TI-SAR ADC with the proposed RASD, the static power dissipation is reduced by 69%. ON-chip and OFF-chip calibration techniques are used to compensate the interchannel error sources. The prototype was fabricated in a 65-nm CMOS process technology. The peak integral nonlinearity and differential nonlinearity are measured as 0.52 and 0.51 LSB, respectively. At 2.5 GS/s, a signal-to-noise and distortion ratio (SNDR) of 18.6/31.9 dB and a spurious-free dynamic range (SFDR) of 23.7/42.1 dBc are measured before and after the calibration at the Nyquist input frequency with 1 Vpp-diff input signal, and the figure of merit is 0.27 pJ/conversion-step. This chip consumes 22 mW at 1.2-V supply and occupies 0.27-mm(2) area.
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