Simultaneous process self-calibration method using TDC for 3D DDR4 DRAM
- Authors
- Oh, Reum; Jang, J.; Kim, J.; Sung, Man Young
- Issue Date
- 23-10월-2014
- Publisher
- INST ENGINEERING TECHNOLOGY-IET
- Citation
- ELECTRONICS LETTERS, v.50, no.22, pp.1579 - 1580
- Indexed
- SCIE
SCOPUS
- Journal Title
- ELECTRONICS LETTERS
- Volume
- 50
- Number
- 22
- Start Page
- 1579
- End Page
- 1580
- URI
- https://scholar.korea.ac.kr/handle/2021.sw.korea/97056
- DOI
- 10.1049/el.2014.1595
- ISSN
- 0013-5194
- Abstract
- Three-dimensional (3D) dynamic random-access memory (DRAM) with TSVs has been proposed due to continuous demands for low-power and high-density memory without IO loading limitation. However, the process difference among the stacked dies causes the timing mismatch of internal signals. To remove signal confliction and reduce signal skews among the stacked dies, the simultaneous process self-calibration scheme is proposed. The stacked dies using the proposed scheme detect the slowest signal among the stacked dies and internal signals are aligned with the slowest signal at the same time. The time for aligned operation is within one read loop and the scheme is turned off after calibration to reduce additional standby current. The 3D double-data rate 4 (DDR4) DRAM using the proposed scheme is operated over 2133 Mbit/s at 1.2 V.
- Files in This Item
- There are no files associated with this item.
- Appears in
Collections - College of Engineering > School of Electrical Engineering > 1. Journal Articles
Items in ScholarWorks are protected by copyright, with all rights reserved, unless otherwise indicated.