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Impact of channel width on back biasing effect in tri-gate MOSFET

Authors
Park, So JeongJeon, Dae-YoungMontes, LaurentBarraud, SylvainKim, Gyu-TaeGhibaudo, Gerard
Issue Date
2월-2014
Publisher
ELSEVIER
Keywords
SOI (silicon on insulator); Electrostatic coupling; Tri-gate MOSFET; Back bias; Channel width variation
Citation
MICROELECTRONIC ENGINEERING, v.114, pp.91 - 97
Indexed
SCIE
SCOPUS
Journal Title
MICROELECTRONIC ENGINEERING
Volume
114
Start Page
91
End Page
97
URI
https://scholar.korea.ac.kr/handle/2021.sw.korea/99434
DOI
10.1016/j.mee.2013.09.016
ISSN
0167-9317
Abstract
The impact of channel width on back biasing effect in n-type tri-gate metal-oxide semiconductor field effect transistor (MOSFET) on silicon-on-insulator (SOI) material was investigated. In narrow device (W-top_eff = 20 nm), the relatively high control of front gate on overall channel leads to the reduced electrostatic coupling between back and front channels as well as the suppression of back bias effects on both channel threshold voltage and the effective mobility, compared to the planar device (W-top_eff = 170 nm). The lower effective mobility with back bias in narrow device was attributed to poorer front channel interface, and, to significant effect of sidewall mobility. The back biasing effect in tri-gate MOSFET was successfully modeled with 2-D numerical simulation. Through the simulation, the mobility results were interpreted as the consequence of two kinds of mobility degradations, i.e. different mobility attenuation along lateral and vertical directions of channel and additional mobility degradation in narrow device due to the effect of sidewall mobility. The potential profile extracted from numerical simulation provides strong evidence showing different degree of electrostatic coupling in narrow device and planar device due to a relative influence of front gate bias control over channels. (C) 2013 Elsevier B.V. All rights reserved.
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공과대학 (전기전자공학부)
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