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김철우 프로필 사진

김철우

KIM, Chul woo

공과대학

전기전자공학부

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연도별 연구 활동 현황

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전체 193건 중 171번부터 180번까지의 결과를 표시합니다.

Conference

Low-Power Small-Area ±7.28 ps Jitter DLL-based Clock Generator

KIM, Chulwoo

Conference

A Fully Differential Phase-Locked Loop for 1.65Ghz, 165Mhz Clock Generation

KIM, Chulwoo

대한민국

Conference

A 64-PE Folded-Torus Intra-chip Communication Fabric for Guaranteed Throughput in Network-on-Chip Based Applications

KIM, Chulwoo

미국

Conference

An Efficient Adaptive Digital DC-DC Converter with Dual Loop Controls for Fast Dynamic Voltage Scaling

KIM, Chulwoo

Conference

A 283.2uW 800Mb/s/pin DLL-Based Data Self-Aligner for Through Silicon Via(TSV) Interface

KIM, Chulwoo

미국

Conference

Current-mode DC-DC Buck Converter with Reliable Hysteretic-Mode Control and Dual Modulator for Fast Dynamic Voltage Scaling

KIM, Chulwoo

멕시코

Conference

A 5.4Gb/S Adaptive Equalizer with Unit Pulse Charging Technique in 0.13μm CMOS

KIM, Chulwoo

미국

Conference

Energy Efficient Skewed Static Logic (S2L) Design with Dual Vt", IEEE International Symposium on Circuits and Systems

KIM, Chulwoo

Conference

A 0.076mm2 3.5GHz Spread-Spectrum Clock Generator with Newton-Raphson Modulation in 0.13um CMOS

KIM, Chulwoo

미국

Conference

A 0.17-1.4GHz Low-Jitter All Digital DLL with TDC-based DCC using Pulse Width Detection Scheme

KIM, Chulwoo

영국

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김철우

자료 필터

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선택된 필터

Low-Power Small-Area ±7.28 ps Jitter DLL-based Clock Generator

A Fully Differential Phase-Locked Loop for 1.65Ghz, 165Mhz Clock Generation

A 64-PE Folded-Torus Intra-chip Communication Fabric for Guaranteed Throughput in Network-on-Chip Based Applications

An Efficient Adaptive Digital DC-DC Converter with Dual Loop Controls for Fast Dynamic Voltage Scaling

A 283.2uW 800Mb/s/pin DLL-Based Data Self-Aligner for Through Silicon Via(TSV) Interface

Current-mode DC-DC Buck Converter with Reliable Hysteretic-Mode Control and Dual Modulator for Fast Dynamic Voltage Scaling

A 5.4Gb/S Adaptive Equalizer with Unit Pulse Charging Technique in 0.13μm CMOS

Energy Efficient Skewed Static Logic (S2L) Design with Dual Vt", IEEE International Symposium on Circuits and Systems

A 0.076mm2 3.5GHz Spread-Spectrum Clock Generator with Newton-Raphson Modulation in 0.13um CMOS

A 0.17-1.4GHz Low-Jitter All Digital DLL with TDC-based DCC using Pulse Width Detection Scheme