Investigation of vertically trapped charge locations in Cr-doped-SrTiO3-based charge trapping memory devices

Abstract

In this paper, vertically trapped charge location is investigated to understand the carrier-transport dynamics in chromium-doped strontium titanate (Cr-SrTiO3 (STO))-based charge trapping memory devices using a transient analysis method. The vertical location of trapped charges is found to move from the Cr-SrTiO3/Si3N4 interface to the bulk region of Si3N4 with an increasing of the electric field, and, particularly, available trap sites are limited at the Cr-SrTiO3/Si3N4 interface by hole injection from the Si substrate into the Si3N4 layer at a high electric field (E-OX > 7 MV/cm). In addition, some of these charges passing across the SiO2 (OX) layer generate many Si-SiO2 interface traps (D-it: 1.58 x 10(12) cm(-2) eV(-1)) that may degrade the device. However, the trapping efficiency can be improved by using sufficiently thick (> 10 nm) bottom layers and by preventing direct hole tunneling and thereby, reducing the interface trap density. (C) 2012 American Institute of Physics. [http://dx.doi.org/10.1063/1.4757413]