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Multiple silicon nanowire complementary tunnel transistors for ultralow-power flexible logic applications

Authors
Lee, M.Jeon, Y.Jung, J-C.Koo, S-M.Kim, S.
Issue Date
18-6월-2012
Publisher
AMER INST PHYSICS
Citation
APPLIED PHYSICS LETTERS, v.100, no.25
Indexed
SCIE
SCOPUS
Journal Title
APPLIED PHYSICS LETTERS
Volume
100
Number
25
URI
https://scholar.korea.ac.kr/handle/2021.sw.korea/108152
DOI
10.1063/1.4729930
ISSN
0003-6951
Abstract
Based on experimental and simulation studies to gain insight into the suppression of ambipolar conduction in two distinct tunnel field-effect transistor (TFET) devices (that is, an asymmetric source-drain doping or a properly designed gate underlap), here we report on the fabrication and electrical/mechanical characterization of a flexible complementary TFET (c-TFET) inverter on a plastic substrate using multiple silicon nanowires (SiNWs) as the channel material. The static voltage transfer characteristic of the SiNW c-TFET inverter exhibits a full output voltage swing between 0 V and V-dd with a high voltage gain of similar to 29 and a sharp transition of 0.28 V at V-dd = 3V. A leakage power consumption of the SiNW c-TFET inverter in the standby state is as low as 17.1 pW for V-dd = 3V. Moreover, its mechanical bendability indicates that it has good fatigue properties, providing an important step towards the realization of ultralow-power flexible logic circuits. (C) 2012 American Institute of Physics. [http://dx.doi.org/10.1063/1.4729930]
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