A Jitter and Power Analysis on DCO
- Authors
- Lee, Doo-Chan; Kim, Kyu-Young; Min, Young-Jae; Park, Jongsun; Kim, Soo-Won
- Issue Date
- 9월-2011
- Publisher
- IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
- Keywords
- All-digital phase-locked loop (ADPLL); clock generator; digitally controlled oscillator (DCO); jitter
- Citation
- IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, v.58, no.9, pp.560 - 564
- Indexed
- SCIE
SCOPUS
- Journal Title
- IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS
- Volume
- 58
- Number
- 9
- Start Page
- 560
- End Page
- 564
- URI
- https://scholar.korea.ac.kr/handle/2021.sw.korea/111616
- DOI
- 10.1109/TCSII.2011.2161161
- ISSN
- 1549-7747
- Abstract
- A jitter and power analysis on a digitally controlled oscillator (DCO) is presented in this brief. By analyzing variable capacitance components on each switching node of the DCO, a simple jitter and power model was derived in a closed form. The proposed mathematical analysis can be effectively used for the accurate and faster estimation of the DCO jitter and power consumption; thus, the overall DCO design time can be significantly reduced. In order to validate our proposed mathematical modeling, the DCO has been designed and fabricated using a 0.13-mu m 1.2-V CMOS process. The fabricated chip presents the root-mean-square and peak-to-peak jitters of 8.9 and 70 ps, respectively, at the output frequency of 600 MHz, under the operation range of 179-656 MHz with a 2.8-ps resolution, which clearly shows that our proposed modeling is well matched with the experimental results.
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