Fast and accurate estimation of SRAM read and hold failure probability using critical point sampling
- Authors
- Chang, I. J.; Park, J.; Kang, K.; Roy, K.
- Issue Date
- 11월-2010
- Publisher
- INST ENGINEERING TECHNOLOGY-IET
- Keywords
- SRAM; SRAM failure analysis
- Citation
- IET CIRCUITS DEVICES & SYSTEMS, v.4, no.6, pp.469 - 478
- Indexed
- SCIE
SCOPUS
- Journal Title
- IET CIRCUITS DEVICES & SYSTEMS
- Volume
- 4
- Number
- 6
- Start Page
- 469
- End Page
- 478
- URI
- https://scholar.korea.ac.kr/handle/2021.sw.korea/115458
- DOI
- 10.1049/iet-cds.2010.0137
- ISSN
- 1751-858X
- Abstract
- Owing to increase in parametric variations with technology scaling, accurate estimation of bit-cell failure probability in nano-scale static random access memory (SRAM) has become an extremely challenging task. In this study, the authors propose a method to detect the SRAM bit-cell failure, named 'critical point sampling'. Using this technique, read and hold failure probability of an SRAM bit-cell can be efficiently estimated in a simulation-based way. Simulation results show that our estimation method provides high accuracy, while being similar to 50x faster in computational speed compared to transient Monte-Carlo simulation. The method can be applied to optimise SRAM design for better yield and contributes significantly in reducing the overall design time.
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