Electrical characteristics of Si-nanoparticle/Si-nanowire-based field-effect transistors
- Authors
- Kang, Jeongmin; Keem, Kihyun; Jeong, Dong-Young; Park, Miyoung; Whang, Dongmok; Kim, Sangsig
- Issue Date
- 5월-2008
- Publisher
- SPRINGER
- Citation
- JOURNAL OF MATERIALS SCIENCE, v.43, no.10, pp.3424 - 3428
- Indexed
- SCIE
SCOPUS
- Journal Title
- JOURNAL OF MATERIALS SCIENCE
- Volume
- 43
- Number
- 10
- Start Page
- 3424
- End Page
- 3428
- URI
- https://scholar.korea.ac.kr/handle/2021.sw.korea/123679
- DOI
- 10.1007/s10853-007-2310-6
- ISSN
- 0022-2461
- Abstract
- In this study, Si-nanoparticle(NP)/Si-nanowire(NW)-based field-effect transistors (FETs) with a top-gate geometry were fabricated and characterized. In these FETs, Si NPs were embedded as localized trap sites in Al2O3 top-gate layers coated on Si NW channels. Drain current versus drain voltage (I-DS-V-DS) and drain current versus gate voltage (I-DS-V-GS) were measured for the Si NP/Si NW-based FETs to investigate their electrical and memory characteristics. The Si NW channels were depleted at V-GS = 9 V, indicating that the devices functioned as p-type depletion-mode FETs. The top-gate Si NW-based FETs decorated with Si NPs show counterclockwise hysteresis loops in the I-DS-V-GS curves, revealing their significant charge storage effect.
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