Detailed Information

Cited 0 time in webofscience Cited 0 time in scopus
Metadata Downloads

Analytical Model of Contact Resistance in Vertically Stacked Nanosheet FETs for Sub-3-nm Technology Node

Authors
Jung, Seung-GeunKim, Jeong-KyuYu, Hyun-Yong
Issue Date
Mar-2022
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Keywords
Contact resistance; contact resistivity; contact size; drain; gate-all around FET (GAAFET); nanosheet FET (NSHFET); silicide; source; spreading resistance
Citation
IEEE TRANSACTIONS ON ELECTRON DEVICES, v.69, no.3, pp.930 - 935
Indexed
SCIE
SCOPUS
Journal Title
IEEE TRANSACTIONS ON ELECTRON DEVICES
Volume
69
Number
3
Start Page
930
End Page
935
URI
https://scholar.korea.ac.kr/handle/2021.sw.korea/140845
DOI
10.1109/TED.2022.3143473
ISSN
0018-9383
Abstract
For the first time, a novel analytical model of contact resistance (R-contact) in vertically stacked nanosheet FETs (NSHFETs) with a silicide/Si (100) contact for a sub-3-nm node is presented. Generally, R-contact consists of the interface resistance(R-interface) and spreading resistance (R-sprea(d)). Herein, a new model of R-interface of silicide/Si (100) contact, which simultaneously considers the source/drain (S/D) doping concentration (N-si), Schottky barrier height (SBH), and SBH lowering, is demonstrated simultaneously. In addition, a new model of R(spread )that divides S/D into multiple resistance components for vertically stacked NSHFETs is suggested. In vertically stacked NSHFET with 3-nm node, for TiSi2/n-Si (100) and NiPtSi2/p-Si (100) contacts, R-spread shows more than similar to 50.0% higher values compared to R-interface. On the other hand, 3-nm node FinFET with TiSi2/n-Si (100) and NiPtSi2/p-Si (100) contacts, R-spread shows more than similar to 53.7% lower values compared to R-contact. The results show that R-spread becomes dominant in R-contact compared to R-interface when using R-s(pread) NSHFETs, in contrast to the conventional FinFETs in which R-interface is dominant in R-contact. The high R-spread of the NSHFET is mainly caused by the low nanosheet thickness and vertical pitch between the nanosheets. This study provides critical insights into the design of the source/drain of NSHFET for sub-3-nm CMOS technology.
Files in This Item
There are no files associated with this item.
Appears in
Collections
College of Engineering > School of Electrical Engineering > 1. Journal Articles

qrcode

Items in ScholarWorks are protected by copyright, with all rights reserved, unless otherwise indicated.

Related Researcher

Researcher Yu, Hyun Yong photo

Yu, Hyun Yong
College of Engineering (School of Electrical Engineering)
Read more

Altmetrics

Total Views & Downloads

BROWSE