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65-nm Si CMOS 공정 기반 123 GHz 위상동기루프 (Phase Locked Loop)65-nm Si CMOS 공정 기반 123 GHz 위상동기루프 (Phase Locked Loop)
- Alternative Title
- 65-nm Si CMOS 공정 기반 123 GHz 위상동기루프 (Phase Locked Loop)
- Authors
- Rieh, Jae-Sung
- Issue Date
- 18-9월-2014
- Publisher
- ieek
- Citation
- 14th RF/Analog Circuit Workshop
- Conference Name
- 14th RF/Analog Circuit Workshop
- Place
- KO
- Conference Date
- 2014-09-18
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Collections - College of Engineering > School of Electrical Engineering > 2. Conference Papers
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