ASPICEmodel of p-channel silicon tunneling field-effect transistors for logic applications
- Authors
- Woo, Sola; Jeon, Juhee; Kim, Sangsig
- Issue Date
- 1월-2021
- Publisher
- WILEY
- Keywords
- device modeling; SPICE model; TCAD simulation; tunnel FET; tunnel FET logic gate
- Citation
- INTERNATIONAL JOURNAL OF NUMERICAL MODELLING-ELECTRONIC NETWORKS DEVICES AND FIELDS, v.34, no.1
- Indexed
- SCIE
SCOPUS
- Journal Title
- INTERNATIONAL JOURNAL OF NUMERICAL MODELLING-ELECTRONIC NETWORKS DEVICES AND FIELDS
- Volume
- 34
- Number
- 1
- URI
- https://scholar.korea.ac.kr/handle/2021.sw.korea/50636
- DOI
- 10.1002/jnm.2793
- ISSN
- 0894-3370
- Abstract
- In this study, we propose a SPICE model ofp-channel silicon tunneling field-effect transistors (TFETs) for logic applications. To verify our model, electrical characteristics of fabricatedp-TFETs are calibrated by utilizing TCAD and SPICE simulations. We simulate various logic gates, such as complementary TFET (c-TFET) inverters,c-TFET NAND gates, andc-TFET NOR gates using our TFET model. Our simulation shows that ac-TFET inverter can be operated atV(DD)as low as 0.3 V and thatc-TFET logic gates based on our model can operate similar to 1000 times higher frequency than conventional TFET logic gates.
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Collections - College of Engineering > School of Electrical Engineering > 1. Journal Articles
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