Analysis of Drain Linear Current Turn-Around Effect in Off-State Stress Mode in pMOSFET

Abstract

The turn-around effect of drain linear current (I-dlin) with stress time in a pMOSFET in the off-state stress is investigated. The degradation rate of I-dlin increases to a maximum of 6.1% at 20 s of the stress time and then continuously decreases to 3.35% at 1000 s in the off-state stress. The turn-around effect is analyzed by comparing the degradation rates of the performance parameters (I-dlin, I-dsat, SS, and V-th) in the off -state and gate induced drain leakage (gidl) -state stress modes. The results indicate that the I-dlin turn-around effect in the off-state stress, which occurs as an effect of the negative oxide charge (Q(ox)) formation, is more significant than that of the interface trap (N-it) for short stress time (before 20 s), and the donor-like N-it formation has major effects compared to those of Q(ox) over a long stress time (after 20 s). This observation shows that the stress-induced trap generation can be investigated even if the protection diode exists and critically impacts the drain current degradation and should be seriously considered in the reliability of a DRAM circuit.