Transposable 3T-SRAM Synaptic Array Using Independent Double-Gate Feedback Field-Effect Transistors
- Authors
- Woo, Sola; Cho, Jinsun; Lim, Doohyeok; Cho, Kyoungah; Kim, Sangsig
- Issue Date
- 11월-2019
- Publisher
- IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
- Keywords
- Transistors; Logic gates; Random access memory; Electric potential; Doping; Feedback loop; Computational modeling; Double-gate; feedback field-effect transistors (FBFETs); static random access memory (SRAM); synapse device; transposable memory
- Citation
- IEEE TRANSACTIONS ON ELECTRON DEVICES, v.66, no.11, pp.4753 - 4758
- Indexed
- SCIE
SCOPUS
- Journal Title
- IEEE TRANSACTIONS ON ELECTRON DEVICES
- Volume
- 66
- Number
- 11
- Start Page
- 4753
- End Page
- 4758
- URI
- https://scholar.korea.ac.kr/handle/2021.sw.korea/62081
- DOI
- 10.1109/TED.2019.2939393
- ISSN
- 0018-9383
- Abstract
- In this article, we present a transposable three-transistor static random access memory (3T-SRAM) array consisting of independent double-gate feedback field-effect transistors as binary synaptic devices and access transistors. The synaptic functions of the ${2} \times {2}$ SRAM array are investigated through mixed-mode technology computer-aided design simulations. This 3T-SRAM array provides parallel and bidirectional synaptic updates with fast operating speed. Furthermore, a simplified spike-timing-dependent plasticity learning rule is implemented by adjusting the widths of memory pulses. A compact cell area and a low-leakage power consumption allow this 3T-SRAM array to be used for adaptive synaptic devices in a large-scale neuromorphic system.
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Collections - College of Engineering > School of Electrical Engineering > 1. Journal Articles
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