Ultralow Schottky Barrier Height Achieved by Using Molybdenum Disulfide/Dielectric Stack for Source/Drain Contact
- Authors
- Kim, Seung-Hwan; Han, Kyu Hyun; Park, Euyjin; Kim, Seung-Geun; Yu, Hyun-Yong
- Issue Date
- 18-Sep-2019
- Publisher
- AMER CHEMICAL SOC
- Keywords
- Schottky barrier height; Fermi-level pinning; molybdenum disulfide; metal-induced gap state; III-V semiconductor; germanium; source/drain contact
- Citation
- ACS APPLIED MATERIALS & INTERFACES, v.11, no.37, pp.34084 - 34090
- Indexed
- SCIE
SCOPUS
- Journal Title
- ACS APPLIED MATERIALS & INTERFACES
- Volume
- 11
- Number
- 37
- Start Page
- 34084
- End Page
- 34090
- URI
- https://scholar.korea.ac.kr/handle/2021.sw.korea/62856
- DOI
- 10.1021/acsami.9b10746
- ISSN
- 1944-8244
- Abstract
- Energy barrier formed at a metal/semiconductor interface is a critical factor determining the performance of nano-electronic devices. Although diverse methods for reducing the Schottky barrier height (SBH) via interface engineering have been developed, it is still difficult to achieve both an ultralow SBH and a low dependence on the contact metals. In this study, a novel structure, namely, a metal/ transition-metal dichalcogenide (TMD) interlayer (IL)/dielectric IL/semiconductor (MTDS) structure, was developed to overcome these issues. Molybdenum disulfide (MoS2) is a promising TMD IL material owing to its interface characteristics, which yields a low SBH and reduces the reliance on contact metals. Moreover, an ultralow SBH is achieved via the insertion of an ultrathin ZnO layer between MoS2 and a semiconductor, thereby inducing an n-type doping effect on the MoS2 IL and forming an interface dipole in the favorable direction at the ZnO IL/semiconductor interfaces. Consequently, the lowest SBH (0.07 eV) and a remarkable improvement in the reverse current density (by a factor of approximately 5400) are achieved, with a wide room for contact-metal dependence. This study experimentally and theoretically validates the effect of the proposed MTDS structure, which can be a key technique for next-generation nanoelectronics.
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