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A Perspective on Test Methodologies for Supervised Machine Learning Accelerators

Authors
Motaman, SeyedhamidrezaGhosh, SwaroopPark, Jongsun
Issue Date
9월-2019
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Keywords
DFT; stuck at fault; neural network; hardware accelerator
Citation
IEEE JOURNAL ON EMERGING AND SELECTED TOPICS IN CIRCUITS AND SYSTEMS, v.9, no.3, pp.562 - 569
Indexed
SCIE
SCOPUS
Journal Title
IEEE JOURNAL ON EMERGING AND SELECTED TOPICS IN CIRCUITS AND SYSTEMS
Volume
9
Number
3
Start Page
562
End Page
569
URI
https://scholar.korea.ac.kr/handle/2021.sw.korea/63056
DOI
10.1109/JETCAS.2019.2933678
ISSN
2156-3357
Abstract
Neural Network (NN) accelerators are essential in many emerging applications e.g., autonomous systems in making mission-critical decisions, health-care solutions to assist with diagnoses, etc. Any soft or hard failure during operation can potentially have catastrophic consequences in many of these applications. For instance, inaccurate classification during object recognition and tracking in autonomous vehicles can lead to crashes and subsequent injuries to the passengers. Therefore, testing Neural Network accelerators to ensure reliability and integrity of the underlying hardware is a crucial task to ensure the functionality, especially the ones that are used in mission-critical applications. Conventional functional, stuck-at and delay tests are not sufficient to characterize the ML systems since they face new test and validation challenges. This paper is aimed to provide a perspective on new test requirements and design for test techniques to cover ML features and detect various type of faults in NN accelerator. We discuss First-In-First-Out (FIFO) and Scratchpad based neural network hardware accelerators and propose test methods to detect the faults as well as fault location in different modules of the accelerator including MAC unit, Activation function module, and Processing Element (PE) registers.
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공과대학 (전기전자공학부)
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