Detailed Information
Cited 0 time in 
Cited 0 time in 
Cited 0 time in
Metadata Downloads
Variation of poly-Si grain structures under thermal annealing and its effect on the performance of TiN/Al2O3/Si3N4/SiO2/poly-Si capacitors
- Authors
- Hong, Suk Bum; Park, Ju Hyun; Lee, Tae Ho; Lim, Jun Hee; Shin, Changhwan; Park, Young Woo; Kim, Tae Geun
- Issue Date
- 31-May-2019
- Publisher
- ELSEVIER SCIENCE BV
- Keywords
- Poly-silicon channel; Interface trap; Grain boundary; TANOS; Rapid thermal annealing
- Citation
- APPLIED SURFACE SCIENCE, v.477, pp.104 - 110
- Indexed
- SCIE
SCOPUS
- Journal Title
- APPLIED SURFACE SCIENCE
- Volume
- 477
- Start Page
- 104
- End Page
- 110
- ISSN
- 0169-4332
- Abstract
- This study presents the improved memory properties of TiN/Al2O3/Si3N4/SiO2/poly-Si (TANOS) capacitors after rapid thermal annealing (RTA) and high-pressure annealing processes (HPAP) using H-2 and D-2 molecules. First, it was confirmed that the recrystallization rate, and thus the grain size of the poly-silicon (poly-Si) film, increased with an increase of the RTA temperature, eventually improving the performance of the TANOS capacitor by reducing the trap densities at the poly-Si/SiO2 interface. Then, it was found that device performance parameters, such as program/erase speed and data retention, could be further improved through HPAP owing to the passivation of band gap states at the poly-Si channel grain boundary. Finally, it was confirmed that these improvements can be observed at a transistor level in the same fashion using the Silvaco TCAD simulation. (C) 2017 Elsevier B.V. All rights reserved.
- Files in This Item
- There are no files associated with this item.
- Appears in
Collections - College of Engineering > School of Electrical Engineering > 1. Journal Articles
Items in ScholarWorks are protected by copyright, with all rights reserved, unless otherwise indicated.
Related Researcher
- Kim, Tae geun
- College of Engineering (School of Electrical Engineering)