Static Random Access Memory Characteristics of Single-Gated Feedback Field-Effect Transistors

Abstract

In this paper, we propose a novel static random access memory (SRAM) unit cell design and its array structure consisting of single-gated feedback field-effect transistors (FBFETs). To verify the SRAM characteristics, the basic memory operations and write disturbances of the unit cell are investigated through the mixed-mode technology computer-aided design simulations. The unit cell exhibits the superior SRAM characteristics including a write speed of 0.6 ns, a fast read-out speed of similar to 0.1 ns, and a retention time of 3600 s. Furthermore, the unit cell design exhibits advantages in density, with a small cell area of 8F(2), and in the power consumption; the standby power consumption is 0.24 nW/bit for holding "1" and negligible for holding "0." Moreover, our SRAM array shows reliable 3 x 3 array operations without any disturbances. This paper demonstrates the promising potential of the FBFET SRAM for high-performance, high-density, and low-power memory applications.