Covered Source-Channel Tunnel Field-Effect Transistors With Trench Gate Structures
- Authors
- Woo, Sola; Kim, Sangsig
- Issue Date
- 2019
- Publisher
- IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
- Keywords
- Tunnel field-effect transistors; TCAD simulation; SPICE model; covered source-channel TFET; trench gate
- Citation
- IEEE TRANSACTIONS ON NANOTECHNOLOGY, v.18, pp.114 - 118
- Indexed
- SCIE
SCOPUS
- Journal Title
- IEEE TRANSACTIONS ON NANOTECHNOLOGY
- Volume
- 18
- Start Page
- 114
- End Page
- 118
- URI
- https://scholar.korea.ac.kr/handle/2021.sw.korea/69021
- DOI
- 10.1109/TNANO.2018.2882859
- ISSN
- 1536-125X
- Abstract
- We propose a new design for covered source-channel tunnel field-effect transistors (CSC-TFETs) with trench gate structures. The I-V characteristics, ON/OFF current ratio, subthreshold swing, and band-to-band tunneling rate are analyzed using a commercial device simulator. Our proposed CSC-TFETs exhibit an ON/OFF current ratio of approximately 10(10), an ON-current of approximately 10(-5) A/mu m at room temperature, and a subthreshold swing of less than 40 mV/decade. In addition, the ON-current of the CSC-TFETs is similar to 233 times that of conventional TFETs, demonstrating that the switching characteristics are superior to those of other silicon-based TFETs. Moreover, a CSC-TFET inverter is characterized by SPICE calibration and provides a high frequency of approximately 1 GHz at a supply voltage of 1.0 V.
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Collections - College of Engineering > School of Electrical Engineering > 1. Journal Articles
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