CMOS 120 GHz Phase-Locked Loops Based on Two Different VCO Topologies
- Authors
- Yoo, Junghwan; Rieh, Jae-Sung
- Issue Date
- 4월-2017
- Publisher
- KOREAN INST ELECTROMAGNETIC ENGINEERING & SCIENCE
- Keywords
- CMOS; Frequency Doubler; Phase-Locked Loop (PLL); Signal Source; Voltage-Controlled Oscillator (VCO)
- Citation
- JOURNAL OF ELECTROMAGNETIC ENGINEERING AND SCIENCE, v.17, no.2, pp.98 - 104
- Indexed
- SCOPUS
KCI
- Journal Title
- JOURNAL OF ELECTROMAGNETIC ENGINEERING AND SCIENCE
- Volume
- 17
- Number
- 2
- Start Page
- 98
- End Page
- 104
- URI
- https://scholar.korea.ac.kr/handle/2021.sw.korea/84064
- DOI
- 10.5515/JKIEES.2017.17.2.98
- ISSN
- 2234-8409
- Abstract
- This work describes the development and comparison of two phase-locked loops (PLLs) based on a 65-nm CMOS technology. The PLLs incorporate two different topologies for the output voltage-controlled oscillator (VCO): LC cross-coupled and differential Colpitts. The measured locking ranges of the LC cross-coupled VCO-based phase-locked loop (PLL1) and the Colpitts VCO-based phase-locked loop (PLL2) are 119.84-122.61 GHz and 126.53-129.29 GHz, respectively. Th e output powers of PLL1 and PLL2 are - 8.6 dBm and -10.5 dBm with DC power consumptions of 127.3 mW and 142.8 mW, respectively. The measured phase noise of PLL1 is -59.2 at 10 kHz offset and -104.5 at 10 MHz offset, and the phase noise of PLL2 is -60.9 dBc/ Hz at 10 kHz offset and -104.4 dBc/Hz at 10 MHz offset. The chip sizes are 1,080 mu m x 760 mu m (PLL1) and 1,100 mu m x 800 mu m (PLL2), including the probing pads.
- Files in This Item
- There are no files associated with this item.
- Appears in
Collections - College of Engineering > School of Electrical Engineering > 1. Journal Articles
Items in ScholarWorks are protected by copyright, with all rights reserved, unless otherwise indicated.