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Fermi-Level Unpinning Using a Ge-Passivated Metal-Interlayer-Semiconductor Structure for Non-Alloyed Ohmic Contact of High-Electron-Mobility Transistors

Authors
Kim, Seung-HwanKim, Gwang-SikKim, Jeong-KyuPark, Jin-HongShin, ChanghwanChoi, ChanghwanYu, Hyun-Yong
Issue Date
Sep-2015
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Keywords
Fermi level unpinning; gallium arsenide; germanium; specific contact resistivity; passivation
Citation
IEEE ELECTRON DEVICE LETTERS, v.36, no.9, pp.884 - 886
Indexed
SCIE
SCOPUS
Journal Title
IEEE ELECTRON DEVICE LETTERS
Volume
36
Number
9
Start Page
884
End Page
886
URI
https://scholar.korea.ac.kr/handle/2021.sw.korea/92587
DOI
10.1109/LED.2015.2453479
ISSN
0741-3106
Abstract
We demonstrate the use of germanium passivation in conjunction with a ZnO interlayer in a metal-interlayer-semiconductor structure in a source/drain (S/D) contact. The Fermi-level pinning problem resulting in the large contact resistances in S/D contacts is effectively alleviated by inserting a thin Ge passivation layer and a ZnO interlayer, passivating the GaAs surface and reducing the metal-induced gap states on the GaAs surface, respectively. The specific contact resistivity for the Ti/ZnO/Ge/n-GaAs (similar to 2 x 10(18) cm(-3)) structure exhibits a similar to 1660x reduction compared with that of a Ti/n-GaAs structure. These results suggest that the proposed structure shows promise as a nonalloyed ohmic contact in high-electron-mobility transistors.
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