Effects of channel width variation on electrical characteristics of tri-gate Junction less transistors
- Authors
- Jeon, Dae-Young; Park, So Jeong; Mouis, Mireille; Barraud, Sylvain; Kim, Gyu-Tae; Ghibaudo, Gerard
- Issue Date
- Mar-2013
- Publisher
- PERGAMON-ELSEVIER SCIENCE LTD
- Keywords
- Junctionless transistors (JLTs); Sidewall gate effect; Effective width; Threshold voltage (V-th); Flat-band voltage (V-fb); Effective mobility (mu(eff)); 2D numerical simulation
- Citation
- SOLID-STATE ELECTRONICS, v.81, pp 58 - 62
- Pages
- 5
- Indexed
- SCI
SCIE
SCOPUS
- Journal Title
- SOLID-STATE ELECTRONICS
- Volume
- 81
- Start Page
- 58
- End Page
- 62
- URI
- https://scholar.korea.ac.kr/handle/2021.sw.korea/103859
- DOI
- 10.1016/j.sse.2013.01.002
- ISSN
- 0038-1101
1879-2405
- Abstract
- The electrical behavior of tri-gate Junctionless transistors (JLTs) depending on top-effective width (W-top_eff) was investigated, experimentally. As decreasing W-top_eff, the amount of bulk neutral channel is relatively getting smaller than that of surface accumulation channel, whereas the channel sidewall gate effect is reinforced. These cause the shrinkage of the shoulder shape on the gate-to-channel capacitance characteristics (C-gc-V-g), resulting in a noticeable change in the effective mobility (mu(eff)) behavior from that in wide JLT devices, an increase of the threshold voltage (V-th), while the flat-band voltage (V-fb) does not change. 2D numerical simulation results, well consistent to the experimental results, confirm the significant sidewall gate effect in the tri-gate JLT devices with a narrow structure. (C) 2013 Elsevier Ltd. All rights reserved.
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