Leakage current mechanisms in sub-50 nm recess-channel-type DRAM cell transistors with three-terminal gate-controlled diodes
- Authors
- Chung, Eun-Ae; Kim, Young-Pil; Nam, Kab-Jin; Lee, Sungsam; Min, Ji-Young; Shin, Yu-Gyun; Choi, Siyoung; Jin, Gyoyoung; Moon, Joo-Tae; Kim, Sangsig
- Issue Date
- 2월-2011
- Publisher
- PERGAMON-ELSEVIER SCIENCE LTD
- Keywords
- Gate-controlled diode; Leakage current; Cell transistor; RCAT; MOSFET
- Citation
- SOLID-STATE ELECTRONICS, v.56, no.1, pp.219 - 222
- Indexed
- SCIE
SCOPUS
- Journal Title
- SOLID-STATE ELECTRONICS
- Volume
- 56
- Number
- 1
- Start Page
- 219
- End Page
- 222
- URI
- https://scholar.korea.ac.kr/handle/2021.sw.korea/113214
- DOI
- 10.1016/j.sse.2010.10.004
- ISSN
- 0038-1101
- Abstract
- We investigated the leakage mechanism in the recently developed DRAM cell transistors having deeply recessed channels for sub-50 nm technology using a gate-controlled diode method. The identification and modeling of the various leakage components in DRAM cell transistors with three-dimensional structures is of great importance for the estimation of their data retention characteristics. Our study reveals that there is a significant difference in the leakage mechanisms of planar and recessed channel MOSFETs, due to their different geometrical aspects. The leakage current at the extended gate-drain overlapping region in recessed channel MOSFETs is of particular importance from the viewpoint of their refresh modeling. The information on the leakage characteristics of three-dimensional DRAM cell transistors obtained herein will be very useful for refresh modeling and future DRAM device designs. (C) 2010 Published by Elsevier Ltd.
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